This article emphasizes on a strategy to design a Super Twisting Sliding Mode Control (STSMC) method. The proposed controller depends on the device of Field Programmable Gate Array (FPGA) for controlling the trajectory of robot manipulator. The gains of the suggested controller are optimized using Chaotic Particle Swarm Optimization (PSO) in MATLAB toolbox software and Simulink environment. Since the control systems speed has an influence on their stability requirements and performance, (FPGA) device is taken in consideration. The proposed control method based on FPGA is implemented using Xilinx block sets in the Simulink. Integrated Software Environment (ISE 14.7) and System Generator are employed to create the file of Bitstream which can be downloaded in the device of FPGA. The results show that the designed controller based of on the FPGA by using System Generator is completely verified the effectiveness of controlling the path tracking of the manipulator and high speed. Simulation results explain that the percentage improvement in the Means Square Error (MSEs) of using the STSMC based FPGA and tuned via Chaotic PSO when compared with the same proposed controller tuned with classical PSO are 17.32 % and 13.98 % for two different cases of trajectories respectively.
The incredible growth of FPGA capabilities in recent years and the new included features have made them more and more attractive for numerous embedded systems. There is however an important shortcoming concerning security of data and design. Data security implies the protection of the FPGA application in the sense that the data inside the circuit and the data transferred to/from the peripheral circuits during the communication are protected. This paper suggests a new method to support the security of any FPGA platform using network processor technology. Low cost IP2022 UBICOM network processor was used as a security shield in front of any FPGA device. It was supplied with the necessary security methods such as AES ciphering engine, SHA-1, HMAC and an embedded firewall to provide confidentiality, integrity, authenticity, and packets filtering features.
Fuzzy PID controller design is still a complex task due to the involvement of a large number of parameters in defining the fuzzy rule base. To reduce the huge number of fuzzy rules required in the normal design for fuzzy PID controller, the fuzzy PID controller is represented as Proportional-Derivative Fuzzy (PDF) controller and Proportional-Integral Fuzzy (PIF) controller connected in parallel through a summer. The PIF controller design has been simplified by replacing the PIF controller by PDF controller with accumulating output. In this paper, the modified Fuzzy PID controller design for bench-top helicopter has been presented. The proposed Fuzzy PID controller has been described using Very High Speed Integrated Circuit Hardware Description Language (VHDL) and implemented using the Field Programmable Gate Array (FPGA) board. The bench-top helicopter has been used to test the proposed controller. The results have been compared with the conventional PID controller and Internal Model Control Tuned PID (IMC-PID) Controller. Simulation results show that the modified Fuzzy PID controller produces superior control performance than the other two controllers in handling the nonlinearity of the helicopter system. The output signal from the FPGA board is compared with the output of the modified Fuzzy PID controller to show that the FPGA board works like the Fuzzy PID controller. The result shows that the plant responses with the FPGA board are much similar to the plant responses when using simulation software based controller.
Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.
In this work, a new architecture is designed for fuzzy logic system. The proposed architecture is implemented on field programed gate array (FPGA). The hardware designed fuzzy systemimproves the excution speed with very high speed up factor using low cost availble kits such as FPGA. The implementation of the proposed architecture uses very low amount of logic elements and logic array blocks as proven when implementing the proposed architucture on FPGA.
Audio encryption has gained popularity in a variety of fields including education, banking over the phone, military, and private audio conferences. Data encryption algorithms are necessary for processing and sending sensitive information in the context of secure speech conversations. In recent years, the importance of security in any communications system has increased. To transfer data securely, a variety of methods have been used. Chaotic system-based encryption is one of the most significant encryption methods used in the field of security. Chaos-based communication is a promising application of chaos theory and nonlinear dynamics. In this research, a chaotic algorithm for the new chaotic chameleon system was proposed, studied, and implemented. The chameleon chaotic system has been preferred to be employed because it has the property of changing from self-excited (SA) to hidden-attractor (HA) which increases the complexity of the system dynamics and gives strength to the encryption algorithm. A chaotic chameleon system is one in which, depending on the parameter values, the chaotic attractor alternates between being a hidden attractor and a self-excited attractor. This is an important feature, so it is preferable to use it in cryptography compared to other types of chaotic systems. This model was first implemented using a Field Programmable Gate Array (FPGA), which is the first time it has been implemented in practical applications. The chameleon system model was implemented using MATLAB Simulink and the Xilinx System Generator model. Self-excited, hidden, and coexisting attractors are shown in the proposed system. Vivado software was used to validate the designs, and Xilinx ZedBoard Zynq-7000 FPGA was used to implement them. The dynamic behavior of the proposed chaotic system was also studied and analysis methods, including phase portrait, bifurcation diagrams, and Lyapunov exponents. Assessing the quality of the suggested method by doing analyses of many quality measures, including correlation, differential signal-to-noise ratio (SNR), entropy, histogram analysis, and spectral density plot. The numerical analyses and simulation results demonstrate how well the suggested method performs in terms of security against different types of cryptographic assaults.
This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.
In medium voltage and high-power drive applications, pulse width modulation (PWM) techniques are widely used to achieve effective speed control of AC motors. In real-time, an industrial drive system requires reduced hardware complexity and low computation time. The reliability of the AC drive can be improved with the FPGA (field programmable gate array) hardware equipped with digital controllers. To improve the performance of AC drives, a new FPGA-based Wavect real-time prototype controller (Xilinx ZYNQ-7000 SoC) is used to verify the effectiveness of the controller. These advanced controllers are capable of reducing computation time and enhancing the drive performance in real- time applications. The comparative performance analysis is carried out for the most commonly used voltage source inverter (VSI)-based PWM techniques such as sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) for three-phase, two-level inverters. The comparative study shows the SVPWM technique utilizes DC bus voltage more effectively and produces less harmonic distortion in terms of higher output voltage, flexible control of output frequency, and reduced harmonic distortion at output voltage for motor control applications. The simulation and hardware results are verified and validated by using MATLAB/Simulink software and FPGA-based Wavect real-time controller respectively.
In this paper, a two-dimensional (2-D) circular-support wavelet transform (2-D CSWT) is presented. 2-D CSWT is a new geometrical image transform, which can efficiently represent images using 2-D circular spectral split schemes (circularly- decomposed frequency subspaces). 2-D all-pass functions and lattice structure are used to produce 1-level circular symmetric 2-D discrete wavelet transform with approximate linear phase 2-D filters. The classical one-dimensional (1-D) analysis Haar filter bank branches H 0 (z) and H 1 (z) which work as low-pass and high-pass filters, respectively are transformed into their 2-D counterparts H 0 (z 1 ,z 2 ) and H 1 (z 1 ,z 2 ) by applying a circular-support version of the digital spectral transformation (DST). The designed 2-D wavelet filter bank is realized in a separable architecture. The proposed architecture is simulated using Matlab program to measure the deflection ratio (DR) of the high frequency coefficient to evaluate its performance and compare it with the performance of the classical 2-D wavelet architecture. The correlation factor between the input and reconstructed images is also calculated for both architectures. The FPGA (Spartan-3E) Kit is used to implement the resulting architecture in a multiplier-less manner and to calculate the die area and the critical path or maximum frequency of operation. The achieved multiplier-less implementation takes a very small area from FPGA Kit (the die area in 3-level wavelet decomposition takes 300 slices with 7% occupation ratio only at a maximum frequency of 198.447 MHz).
Nowadays, renewable energy is being used increasingly because of the global warming and destruction of the environment. Therefore, the studies are concentrating on gain of maximum power from this energy such as the solar energy. A sun tracker is device which rotates a photovoltaic (PV) panel to the sun to get the maximum power. Disturbances which are originated by passing the clouds are one of great challenges in design of the controller in addition to the losses power due to energy consumption in the motors and lifetime limitation of the sun tracker. In this paper, the neuro-fuzzy controller has been designed and implemented using Field Programmable Gate Array (FPGA) board for dual axis sun tracker based on optical sensors to orient the PV panel by two linear actuators. The experimental results reveal that proposed controller is more robust than fuzzy logic controller and proportional- integral (PI) controller since it has been trained offline using Matlab tool box to overcome those disturbances. The proposed controller can track the sun trajectory effectively, where the experimental results reveal that dual axis sun tracker power can collect 50.6% more daily power than fixed angle panel. Whilst one axis sun tracker power can collect 39.4 % more daily power than fixed angle panel. Hence, dual axis sun tracker can collect 8 % more daily power than one axis sun tracker .
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.
Recently, chaos theory has been widely used in multimedia and digital communications due to its unique properties that can enhance security, data compression, and signal processing. It plays a significant role in securing digital images and protecting sensitive visual information from unauthorized access, tampering, and interception. In this regard, chaotic signals are used in image encryption to empower the security; that’s because chaotic systems are characterized by their sensitivity to initial conditions, and their unpredictable and seemingly random behavior. In particular, hyper-chaotic systems involve multiple chaotic systems interacting with each other. These systems can introduce more randomness and complexity, leading to stronger encryption techniques. In this paper, Hyper-chaotic Lorenz system is considered to design robust image encryption/ decryption system based on master-slave synchronization. Firstly, the rich dynamic characteristics of this system is studied using analytical and numerical nonlinear analysis tools. Next, the image secure system has been implemented through Field-Programmable Gate Arrays (FPGAs) Zedboard Zynq xc7z020-1clg484 to verify the image encryption/decryption directly on programmable hardware Kit. Numerical simulations, hardware implementation, and cryptanalysis tools are conducted to validate the effectiveness and robustness of the proposed system.
Nowadays, multimedia communication has become very widespread and this requires it to be protected from attackers and transmitted securely for reliability. Encryption and decryption techniques are useful in providing effective security for speech signals to ensure that these signals are transmitted with secure data and prevent third parties or the public from reading private messages. Due to the rapid improvement in digital communications over the recent period up to the present, the security of voice data transmitted over various networks has been classified as a favored field of study in earlier years. The contributions to audio encryption are discussed in this review. This Comprehensive review mainly focuses on presenting several kinds of methods for audio encryption and decryption the analysis of these methods with their advantages and disadvantages have been investigated thoroughly. It will be classified into encryption based on traditional methods and encryption based on advanced chaotic systems. They are divided into two types, continuous-time system, and discrete-time system, and also classified based on the synchronization method and the implementation method. In the fields of information and communications security, system designers face many challenges in both cost, performance, and architecture design, Field Programmable gate arrays (FPGAs) provide an excellent balance between computational power and processing flexibility. In addition, encryption methods will be classified based on Chaos-based Pseudo Random Bit Generator, Fractional-order systems, and hybrid chaotic generator systems, which is an advantageous point for this review compared with previous ones. Audio algorithms are presented, discussed, and compared, highlighting important advantages and disadvantages. Audio signals have a large volume and a strong correlation between data samples. Therefore, if traditional cryptography systems are used to encrypt such huge data, they gain significant overhead. Standard symmetric encryption systems also have a small key-space, which makes them vulnerable to attacks. On the other hand, encryption by asymmetric algorithms is not ideal due to low processing speed and complexity. Therefore, great importance has been given to using chaotic theory to encode audio files. Therefore, when proposing an appropriate encryption method to ensure a high degree of security, the key space, which is the critical part of every encryption system, and the key sensitivity must be taken into account. The key sensitivity is related to the initial values and control variables of the chaotic system chosen as the audio encryption algorithm. In addition, the proposed algorithm should eliminate the problems of periodic windows, such as limited chaotic range and non-uniform distribution, and the quality of the recovered audio signal remains good, which confirms the convenience, reliability, and high security.
Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.