Arc problems are most commonly caused by electrical difficulties such as worn cables and improper connections. Electrical fires are caused by arc faults, which generate tremendous temperatures and discharge molten metal. Every year, flames of this nature inflict a great lot of devastation and loss. A novel approach for identifying residential series and parallel arc faults is presented in this study. To begin, arc faults in series and parallel are simulated using a suitable simulation arc model. The fault characteristics are then recovered using a signal processing technique based on the fault detection technique called Discrete Wavelet Transform (DWT), which is built in MATLAB/Simulink. Then came db2, and one level was discovered for obtaining arc-fault features. The suitable mother and level of wavelet transform should be used, and try to compare results with conventional methods (FFT-Fast Fourier Transform). MATLAB was used to build and simulate arc-fault models with these techniques.
The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.
In recent years, symbolic analysis has become a well-established technique in circuit analysis and design. The symbolic expression of network characteristics offers convenience for frequency response analysis, sensitivity computation, and fault diagnosis. The aim of the paper is to present a method for symbolic analysis that depends on the use of the wavelet transform (WT) as a tool to accelerate the solution of the problem as compared with the numerical interpolation method that is based on the use of the fast Fourier transform (FFT).
In recent years, symbolic analysis has become a well-established technique in circuit analysis and design. The symbolic expression of network characteristics offers convenience for frequency response analysis, sensitivity computation, and fault diagnosis. The aim of the paper is to present a method for symbolic analysis that depends on the use of the wavelet transform (WT) as a tool to accelerate the solution of the problem as compared with the numerical interpolation method that is based on the use of the fast Fourier transform (FFT).
Fast and accurate frequency estimation is essential in various engineering applications, including control systems, communications, and resonance sensing systems. This study investigates the effect of sample size on the interpolation algorithm of frequency estimation. In order to enhance the accuracy of frequency estimation and performance, we describe a novel method that provides a number of approaches for calculating and defending the sample size for of the window function designs, whereas, the correct choice of the type and the size of the window function makes it possible to reduce the error. Computer simulation using Matlab / Simulink environment is performed to investigate the proposed procedure’s performance and feasibility. This study performs the comparison of the interpolation algorithm of frequency estimation strategies that can be applied to improve the accuracy of the frequency estimation. Simulation results shown that the proposed strategy with the Parzen and Flat-top gave remarkable change in the maximum error of frequency estimation. They perform better than the conventional windows at a sample size equal to 64 samples, where the maximum error of frequency estimation is 2.13e-2 , and 2.15e-2 for Parzen and Flat-top windows, respectively. Moreover, the efficiency and performance of the Nuttall window also perform better than other windows, where the maximum error is 7.76×10-5 at a sample size equal to 8192. The analysis of simulation result showed that when using the proposed strategy to improve the accuracy of the frequency estimation, it is first essential to evaluate what is the maximum number of samples that can be obtained, how many spectral lines should be used in the calculations, and only after that choose a suitable window.