FPGA-Based Implementation of a Basic Background Subtraction Algorithm for Real-Time Application - Al-Yoonus, Marwan; Al-Kazzaz, Dr. Saad (Iraqi Journal for Electrical and Electronic Engineering, 2025)
An intelligent video system’s basic function is the detection of moving objects. Moreover, real-time systems frequentlypose limitations for applications involving video processing. Practically, to increase the frame rate or in the case oflimited hardware resources, the real-time processing is done on an interested image segment called the region of interest(ROI). Applying the background subtraction (BGS) algorithm to this region is considered the main preprocessingoperation. This paper presents a practical study for video processing based on FPGA to detect moving objects usingthe BGS technique. The proposed algorithm was developed using Verilog hardware description language (HDL),synthesized, and implemented in the programmable logic (PL) part of the ZYBO-7Z010CLG400-1 platform. FiniteState Machine (FSM) controller method was used to design the Intellectual Property (IP) module that controls datatransfer with BRAM (loading and reading) of the input and reference image. The simulation results of the timing signalsequences of the proposed IP module with the practical test of the BGS to detect several traffic signs of image size (90×90)pixels demonstrate that the module functions as intended. The system that is being presented has a latency of 13.468nanoseconds, making it appropriate for real-time applications.