Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic - Hussein, Fatima; AL-Assfor, Fatemah (Iraqi Journal for Electrical and Electronic Engineering, 2025)
Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G,deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC(I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhancedBrent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then,developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MACarchitecture. The proposed multimode MAC block supports three modes of operation; single 64-bit MAC operation, dual32-bit multiplication with 32-bit single addition, and single 32-bit MAC operation. The design has utilized an adjustedarchitecture for the Vedic-multiplier (Adjusted-VM), a 64-bit HBK-CSLA, and a control circuit to select the desiredmode of operation. The performance of the multi-mode MAC is then optimized by exploiting pipelining concept. Theproposed architectures are synthesized in various FPGA families utilizing VHDL language in Xilinx ISE14.7 tool. Theperformance results have exposed that the proposed 64-bit I-MAC block have attained observable lessen 9.767% in delayand area usage of 47.49% compared with the most existing MAC block designs.